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| SH7280 Datasheet, PDF (262/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family | |||
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Section 8 Data Transfer Controller (DTC)
Table 8.10 Number of Cycles Required for Each Execution State
Object to be Accessed
On-Chip
RAM*1
On-Chip
ROM*2
On-Chip I/O Registers
External Device*5
Bus width
32 bits
32 bits
8 bits*4
16 bits
8 bits 16 bits 32 bits
Access cycles
1BÏ to 3BÏ*1 3BÏ to 4IÏ + 2PÏ
2PÏ
2BÏ
2BÏ
2BÏ
3BÏ*2
Exe- Vector read S
I
cution
1BÏ to 3BÏ*1 3BÏ to 4IÏ + 

9BÏ
5BÏ
3BÏ
3BÏ*2
status Transfer information read 1BÏ to 3BÏ*1 


9BÏ
5BÏ
3BÏ
SJ
Transfer information write 1BÏ to 3BÏ*1 
S
k


2BÏ*6 2BÏ*6 2BÏ*6
Byte data read S
L
1BÏ to 3BÏ*1 
1BÏ + 2PÏ*3 1BÏ + 2PÏ*3 3BÏ
3BÏ
3BÏ
Word data read S
L
1BÏ to 3BÏ*1 

1BÏ + 2PÏ*3 5BÏ
3BÏ
3BÏ
Longword data read S
L
1BÏ to 3BÏ*1 

1BÏ + 2PÏ*3 9BÏ
5BÏ
3BÏ
Byte data write S
M
1BÏ to 3BÏ*1 
1BÏ + 2PÏ*3 1BÏ + 2PÏ*3 2BÏ*6 2BÏ*6 2BÏ*6
Word data write S
M
1BÏ to 3BÏ*1 

1BÏ + 2PÏ*3 2BÏ*6 2BÏ*6 2BÏ*6
Longword data write S
M
1BÏ to 3BÏ*1


1BÏ + 2PÏ*3 2BÏ*6 2BÏ*6 2BÏ*6
Internal operation SN
1
Notes: 1. Values for on-chip RAM. Number of cycles varies depending on the ratio of IÏ:BÏ.
IÏ:BÏ = 1:1
IÏ:BÏ = 1:1/2
IÏ:BÏ = 1:1/4
IÏ:BÏ = 1:1/8
Read
3BÏ
2BÏ
2BÏ
1BÏ
Write
2BÏ
2BÏ
2BÏ
1BÏ
2. Values for on-chip ROM. Number of cycles varies depending on the ratio of IÏ:BÏ.
Read
Write
IÏ:BÏ = 1:1
4IÏ + 3BÏ
4IÏ + 3BÏ
IÏ:BÏ = 1:1/2
4IÏ + 3BÏ
4IÏ + 3BÏ
IÏ:BÏ = 1:1/4
4IÏ + 3BÏ
4IÏ + 3BÏ
IÏ:BÏ = 1:1/8
3BÏ
3BÏ
Rev. 1.00 Jun. 26, 2008 Page 232 of 1692
REJ09B0393-0100
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