SH7280 Datasheet, PDF (1546/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 29 User Debugging Interface (H-UDI)
Bit
15 to 8
7 to 2
1
0
Bit Name Initial Value
TI[7:0]
11101111*

All 1

0

1
R/W Description
R
Test Instruction
The H-UDI instruction is transferred to SDIR by a
serial input from TDI.
For commands, see table 29.3.
R
Reserved
These bits are always read as 1.
R
Reserved
This bit is always read as 0.
R
Reserved
This bit is always read as 1.
Table 29.3 H-UDI Commands
Bits 15 to 8
TI7 TI6 TI5 TI4 TI3 TI2 TI1 TI0 Description
0
1
1
0
—
—
—
—
H-UDI reset negate
0
1
1
1
—
—
—
—
H-UDI reset assert
1
0
0
1
1
1
0
0
TDO change timing switch
1
0
1
1
—
—
—
—
H-UDI interrupt
1
1
1
1
—
—
—
—
BYPASS mode
Other than above
Reserved
Rev. 1.00 Jun. 26, 2008 Page 1516 of 1692
REJ09B0393-0100