SH7280 Datasheet, PDF (393/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
T1
T2
CK
A25 to A0
CSn
WEn
RD/WR
Read
RD
D15 to D0
RD/WR
Write
RD
D15 to D0
High
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.36 Basic Access Timing for SRAM with Byte Selection (BAS = 0)
Rev. 1.00 Jun. 26, 2008 Page 363 of 1692
REJ09B0393-0100