SH7280 Datasheet, PDF (263/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 8 Data Transfer Controller (DTC)
3. The values in the table are those for the fastest case. Depending on the state of the
internal bus, replace 1Bφ by 1Pφ in a slow case.
4. Value for I²C2.
5. Values are different depending on the BSC register setting. The values in the table are
the sample for the case with no wait cycles and the WM bit in CSnWCR = 1.
6. Values are different depending on the bus state.
The number of cycles increases when many external wait cycles are inserted in the
case where writing is frequently executed, such as block transfer, and when the
external bus is in use because the write buffer cannot be used efficiently in such cases.
For details on the write buffer, see section 9.5.12 (2), Access from the Side of the LSI
Internal Bus Master.
The number of execution cycles is calculated from the formula below. Note that Σ means the sum
of cycles for all transfers initiated by one activation event (the number of 1-valued CHNE bits in
transfer information plus 1).
Number of execution cycles = I ^• S_I + Σ (J ^• S_J + K ^• S_K + L ^• S_L + M ^• S_M) + N ^• S_N
8.5.9 DTC Bus Release Timing
The DTC requests the bus mastership to the bus arbiter when an activation request occurs. The
DTC releases the bus after a vector read, NOP execution after vector read, transfer information
read, a single data transfer, or transfer information write-back. The DTC does not release the bus
mastership during transfer information read, a single data transfer, or write-back of transfer
information.
The bus release timing can be specified through the bus function extending register (BSCEHR).
For details see section 9.4.8, Bus Function Extending Register (BSCEHR). The difference in bus
release timing according to the register setting is summarized in table 8.11. Settings other than
shown in the table are prohibited. The value of BSCEHR must not be modified while the DTC is
active.
Figure 8.16 is a timing chart showing an example of bus release timing.
Rev. 1.00 Jun. 26, 2008 Page 233 of 1692
REJ09B0393-0100