SH7280 Datasheet, PDF (1659/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

CK
A25 to A0
A12/A11^*1
Tp
Tpw
Trr
t_AD1
t_AD1
t_AD1
t_AD1
CSn
RD/WR
RASU/L
CASU/L
t_CSD1
t_CSD1
t_CSD1
t_CSD1
t_RWD1
t_RWD1
t_RASD1
t_RASD1
t_RASD1
t_RASD1
t_CASD1
t_CASD1
Section 31 Electrical Characteristics
Trc
Trc
Trc
t_RWD1
DQMxx
D31 to D0
(Hi-Z)
BS
CKE
DACKn
TENDn*²
t_CKED1
t_CKED1
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.34 Synchronous DRAM Self-Refreshing Timing
(WTRP = 1 Cycle)
Rev. 1.00 Jun. 26, 2008 Page 1629 of 1692
REJ09B0393-0100