SH7280 Datasheet, PDF (512/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name Value R/W Description
1
CMFV5
0
R/(W)*¹ Compare Match/Input Capture Flag V5
Status flag that indicates the occurrence of TGRV_5 input
capture or compare match.
[Clearing condition]
• When DTC is activated by TGIV_5 interrupt, and the
DISEL bit of MRB in DTC is cleared to 0.
• When 0 is written to CMFV5 after reading CMFV5 = 1
[Setting conditions]
• When TCNTV_5 = TGRV_5 and TGRV_5 is
functioning as output compare register
• When TCNTV_5 value is transferred to TGRV_5 by
input capture signal and TGRV_5 is functioning as
input capture register
• When TCNTV_5 value is transferred to TGRV_5 and
TGRV_5 is functioning as a register for measuring the
pulse width of the external input signal. The transfer
timing is specified by the IOC bits in timer I/O control
registers U_5, V_5, and W_5 (TIORU_5, TIORV_5,
and TIORW_5).*²
Rev. 1.00 Jun. 26, 2008 Page 482 of 1692
REJ09B0393-0100