SH7280 Datasheet, PDF (738/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 13 Port Output Enable 2 (POE2)
13.3.7 Port Output Enable Control Register 1 (POECR1)
POECR1 is an 8-bit readable/writable register that controls high-impedance state of the pins.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
MTU2 MTU2 MTU2 MTU2
PE3ZE PE2ZE PE1ZE PE0ZE
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R/W* R/W* R/W* R/W*
Note: * Can be modified only once after a power-on reset.
Bit
Bit Name
7 to 4 —
Initial
Value
All 0
3
MTU2PE3ZE 0
2
MTU2PE2ZE 0
1
MTU2PE1ZE 0
R/W
R
R/W*
R/W*
R/W*
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
MTU2PE3 High-Impedance Enable
Specifies whether to place the PE3/TIOC0D pin for
channel 0 in the MTU2 in high-impedance state when
either POE8F or MTU2CH0HIZ bit is set to 1.
0: Does not place the pin in high-impedance state
1: Places the pin in high-impedance state
MTU2PE2 High-Impedance Enable
Specifies whether to place the PE2/TIOC0C pin for
channel 0 in the MTU2 in high-impedance state when
either POE8F or MTU2CH0HIZ bit is set to 1.
0: Does not place the pin in high-impedance state
1: Places the pin in high-impedance state
MTU2PE1 High-Impedance Enable
Specifies whether to place the PE1/TIOC0B pin for
channel 0 in the MTU2 in high-impedance state when
either POE8F or MTU2CH0HIZ bit is set to 1.
0: Does not place the pin in high-impedance state
1: Places the pin in high-impedance state
Rev. 1.00 Jun. 26, 2008 Page 708 of 1692
REJ09B0393-0100