SH7280 Datasheet, PDF (444/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 10 Direct Memory Access Controller (DMAC)
Table 10.8 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits
CHCR DMARS DMA Transfer
Request
RS[3:0] MID RID Source
DMA Transfer
Request Signal
Transfer
Source
Transfer Bus
Destination Mode
1000
100000 01 USB receive
10 USB transmit
EP1 FIFO full transfer request USBEPDR1 Any
Cycle
EP2 FIFO empty transfer request Any
USBEPDR2 ^steal
100001 10 RCAN
RM0 (RCAN receive interrupt) MB0 to
Any
MB31
Cycle
steal
100010 01 SSU transmit SSTXI (transmit data empty)
Any
SSTDR0 to Cycle
SSTDR3 steal
10 SSU receive SSRXI (receive data full)
SSRDR0 to Any
SSRDR3
100011 01 SCIF_3 transmit TXI3 (transmit FIFO data empty) Any
SCFTDR3 Cycle
10 SCIF_3 receive RXI3 (receive FIFO data full)
SCFRDR3 Any
steal
101000 01 IIC3 transmit
10 IIC3 receive
TXI (transmit data empty)
RXI (receive data full)
Any
ICDRR
ICDRT
Any
Cycle
steal
101100 11 A/D converter_0 ADI0 (A/D conversion end)
ADDR0 to Any
ADDR3
Cycle
steal
111000 11 MTU2_0
111001 11 MTU2_1
111010 11 MTU2_2
TGI0A
TGI1A
TGI2A
Any
Any
Cycle
Any
Any
steal or
burst
Any
Any
111011 11 MTU2_3
TGI3A
Any
Any
111100 11 MTU2_4
TGI4A
Any
Any
111110 11 CMT_0
111111 11 CMT_1
Compare match 0
Compare match 1
Any
Any
Cycle
Any
Any
steal or
burst
Rev. 1.00 Jun. 26, 2008 Page 414 of 1692
REJ09B0393-0100