SH7280 Datasheet, PDF (1692/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Appendix
Pin Function
Pin State
Reset State
Power-Down State
Type
Pin Name
Power-On
Expansion
without ROM _{Expansion Single-}
8 bits 16 bits ^{with ROM chip} Manual Software Standby
Bus
Master- Oscillation POE
ship Stop
Function
Sleep Release Detected Used
I/O Port
PE9, PE11 to Z
PE15
I/O
Z
I/O I/O
I/O*⁷
Z
(MZIZEH in HCPCR = 0)
K*¹
(MZIZEH in HCPCR = 1)
PF0 to PF7
Z
I
Z
I
I
I
I
[Legend]
I:
Input
O: Output
H: High-level output
L:
Low-level output
Z:
High-impedance
K:
Input pins become high-impedance, and output pins retain their state.
Notes: 1. Output pins become high-impedance when the HIZ bit in standby control register 3
(STBCR3) is set to 1.
2. Becomes output when the HIZCNT bit in the common control register (CMNCR) is set
to 1.
3. Becomes output when the HIZMEM bit in the common control register (CMNCR) is set
to 1.
4. Becomes output when the HIZCKIO bit in the common control register (CMNCR) is set
to 1.
5. Becomes high-impedance when the MZIZDH bit in the high-current port control register
(HCPCR) is cleared to 0.
6. Becomes high-impedance when the MZIZDL bit in the high-current port control register
(HCPCR) is cleared to 0.
7. Becomes high-impedance when the MZIZEH bit in the high-current port control register
(HCPCR) is cleared to 0.
8. Becomes high-impedance when the MZIZEL bit in the high-current port control register
(HCPCR) is cleared to 0.
9. Becomes input during a power-on reset. Pull-up to prevent erroneous operation. Pull-
down with a resistance of at least 1 MΩ as required.
10. Pulled-up inside the LSI when there is no input.
Rev. 1.00 Jun. 26, 2008 Page 1662 of 1692
REJ09B0393-0100