SH7280 Datasheet, PDF (22/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 19 I²C Bus Interface 3 (IIC3).................................................................. 925
19.1 Features............................................................................................................................. 925
19.2 Input/Output Pins.............................................................................................................. 927
19.3 Register Descriptions........................................................................................................ 928
19.3.1 I²C Bus Control Register 1 (ICCR1)................................................................. 929
19.3.2 I²C Bus Control Register 2 (ICCR2)................................................................. 932
19.3.3 I²C Bus Mode Register (ICMR)........................................................................ 934
19.3.4 I²C Bus Interrupt Enable Register (ICIER)....................................................... 936
19.3.5 I²C Bus Status Register (ICSR)......................................................................... 938
19.3.6 Slave Address Register (SAR).......................................................................... 941
19.3.7 I²C Bus Transmit Data Register (ICDRT) ........................................................ 941
19.3.8 I²C Bus Receive Data Register (ICDRR).......................................................... 942
19.3.9 I²C Bus Shift Register (ICDRS)........................................................................ 942
19.3.10 NF2CYC Register (NF2CYC).......................................................................... 943
19.4 Operation .......................................................................................................................... 944
19.4.1 I²C Bus Format.................................................................................................. 944
19.4.2 Master Transmit Operation............................................................................... 945
19.4.3 Master Receive Operation ................................................................................ 947
19.4.4 Slave Transmit Operation ................................................................................. 949
19.4.5 Slave Receive Operation................................................................................... 952
19.4.6 Clocked Synchronous Serial Format ................................................................ 954
19.4.7 Noise Filter ....................................................................................................... 958
19.4.8 Example of Use................................................................................................. 959
19.5 Interrupt Requests............................................................................................................. 963
19.6 Data Transfer Using DTC................................................................................................. 964
19.7 Bit Synchronous Circuit.................................................................................................... 965
19.8 Usage Notes ...................................................................................................................... 968
19.8.1 Setting for Multi-Master Operation .................................................................. 968
19.8.2 Note on Master Receive Mode ......................................................................... 968
19.8.3 Note on Setting ACKBT in Master Receive Mode........................................... 968
19.8.4 Note on the States of Bits MST and TRN when Arbitration Is Lost................. 969
Section 20 A/D Converter (ADC) ....................................................................... 971
20.1 Features............................................................................................................................. 971
20.2 Input/Output Pins.............................................................................................................. 974
20.3 Register Descriptions........................................................................................................ 975
20.3.1 A/D Control Registers 0 to 2 (ADCR_0 to ADCR_2)...................................... 977
20.3.2 A/D Status Registers 0 to 2 (ADSR_0 to ADSR_2) ......................................... 980
20.3.3 A/D Start Trigger Select Registers 0 to 2 (ADSTRGR_0 to ADSTRGR_2).... 981
Rev. 1.00 Jun. 26, 2008 Page xxii of xxx