SH7280 Datasheet, PDF (1635/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 31 Electrical Characteristics
Bφ = 50 MHz*
Item
Symbol Min.
Max.
Unit Figure
CAS delay time 1
t
1
CASD1
20
ns Figures 31.19 to
31.35
CAS delay time 2
DQM delay time 1
t_CASD2
t_DQMD1
1/2t_cyc + 1
1
1/2t_cyc + 20
ns
Figures 31.36, 31.37
20
ns Figures 31.19 to
31.32
DQM delay time 2
t
DQMD2
CKE delay time 1
t
CKED1
CKE delay time 2
t
CKED2
AH delay time
t_AHD
Multiplexed address delay t
MAD
time
1/2t + 1
cyc
1
1/2t + 1
cyc
1/2t_cyc + 1
–
1/2t + 20 ns Figures 31.36, 31.37
cyc
20
ns Figure 31.34
1/2t + 20 ns Figure 31.37
cyc
1/2t_cyc + 20
ns
Figure 31.15
20
ns Figure 31.15
Multiplexed address hold t_MAH
1
time

ns Figure 31.15
DACK, TEND delay time t
DACD

Refer to
ns Figures 31.10 to
peripheral
31.31, 31.35, 31.37
modules
FRAME delay time
t
1
FMD
20
ns Figure 31.16
Note: * The maximum value (f_max) of Bφ (external bus clock) depends on the number of wait
cycles and the system configuration of your board.
Rev. 1.00 Jun. 26, 2008 Page 1605 of 1692
REJ09B0393-0100