SH7280 Datasheet, PDF (661/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
TSR write cycle
T1
T2
Pφ
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 11.116 Timing for Status Flag Clearing by CPU (Channel 5)
Pφ, Bφ
DMAC read cycle
DMAC write cycle
Address
Source address
Destination
address
Status flag
Interrupt
request signal
Flag clear
signal
Figure 11.117 Timing for Status Flag Clearing by DTC Activation (Channels 0 to 4)
Rev. 1.00 Jun. 26, 2008 Page 631 of 1692
REJ09B0393-0100