SH7280 Datasheet, PDF (31/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 1 Overview
Section 1 Overview
1.1 SH7286, SH7285, and SH7243 Features
This LSI is a single-chip RISC microprocessor that integrates a Renesas Technology original
RISC CPU core with peripheral functions required for system configuration.
The CPU in this LSI has a RISC-type (Reduced Instruction Set Computer) instruction set and uses
a superscalar architecture and a Harvard architecture, which greatly improves instruction
execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power.
With this CPU, it has become possible to assemble low-cost, high-performance, and high-
functioning systems, even for applications that were previously impossible with microprocessors,
such as realtime control, which demands high speeds.
In addition, this LSI includes on-chip peripheral functions necessary for system configuration,
such as a large-capacity ROM, a ROM cache, a RAM, a direct memory access controller
(DMAC), a data transfer controller (DTC), multi-function timer pulse units 2 (MTU2 and
MTU2S), a serial communication interface with FIFO (SCIF), a serial communication interface
(SCI), a synchronous serial communication interface (SSU), an A/D converter, a D/A converter,
an interrupt controller (INTC), I/O ports, I²C bus interface 3 (IIC3), a universal serial bus (USB),
and a controller area network (RCAN-ET).
This LSI also provides an external memory access support function to enable direct connection to
various memory devices or peripheral LSIs.
These on-chip functions significantly reduce costs of designing and manufacturing application
systems.
The features of this LSI are listed in table 1.1.
Rev. 1.00 Jun. 26, 2008 Page 1 of 1692
REJ09B0393-0100