SH7280 Datasheet, PDF (180/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 6 Interrupt Controller (INTC)
Number of States
Item
NMI
UBC
H-UDI
IRQ
Peripheral
Module
Remarks
Interrupt
response
time
No register Min.
banking
5 Icyc +
2 Bcyc +
1 Pcyc +
m1 + m2
6 Icyc +
m1 + m2
5 Icyc +
1 Pcyc +
m1 + m2
5 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc +
1 Bcyc +
1 Pcyc +
m1 + m2
100-MHz operation*¹*²:
0.080 to 0.150 µs
Max.
6 Icyc +
2 Bcyc +
1 Pcyc +
2(m1 + m2) +
m3
7 Icyc +
2(m1 + m2) +
m3
6 Icyc +
1 Pcyc +
2(m1 + m2) +
m3
6 Icyc +
3 Bcyc +
1 Pcyc +
2(m1 + m2) +
m3
6 Icyc +
1 Bcyc +
1 Pcyc +
2(m1 + m2) +
m3
100-MHz operation*¹*²:
0.120 to 0.190 µs
Register Min.
—
—
5 Icyc +
5 Icyc +
5 Icyc +
100-MHz operation*¹*²:
banking
1 Pcyc +
3 Bcyc +
1 Bcyc +
0.080 to 0.150 µs
without
m1 + m2
1 Pcyc +
1 Pcyc +
register
m1 + m2
m1 + m2
bank
Max. —
—
14 Icyc +
14 Icyc +
14 Icyc +
100-MHz operation*¹*²:
overflow
1 Pcyc +
3 Bcyc +
1 Bcyc +
0.170 to 0.240 µs
m1 + m2
1 Pcyc +
1 Pcyc +
m1 + m2
m1 + m2
Register Min.
—
—
5 Icyc +
5 Icyc +
5 Icyc +
100-MHz operation*¹*²:
banking
1 Pcyc +
3 Bcyc +
1 Bcyc +
0.080 to 0.150 µs
with
m1 + m2
1 Pcyc +
1 Pcyc +
register
m1 + m2
m1 + m2
bank
Max. —
—
5 Icyc +
5 Icyc +
5 Icyc +
100-MHz operation*¹*²:
overflow
1 Pcyc +
3 Bcyc +
1 Bcyc +
0.270 to 0.340 µs
m1 + m2 + 1 Pcyc +
1 Pcyc +
19(m4)
m1 + m2 + m1 + m2 +
19(m4)
19(m4)
Notes: m1 to m4 are the number of states needed for the following memory accesses.
m1: Vector address read (longword read)
m2: SR save (longword write)
m3: PC save (longword write)
m4: Banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the
stack.
1. In the case that m1 = m2 = m3 = m4 = 1 Icyc.
2. In the case that (Iφ, Bφ, Pφ) = (100 MHz, 50 MHz, 50 MHz).
Rev. 1.00 Jun. 26, 2008 Page 150 of 1692
REJ09B0393-0100