SH7280 Datasheet, PDF (1520/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 27 On-Chip RAM
• Ports
Each page has two independent read and write ports and is connected to the internal bus (I
bus), CPU instruction fetch bus (F bus), and CPU memory access bus (M bus). (Note that the F
bus is connected only to the read ports.)
The F bus and M bus are used for access by the CPU, and the I bus is used for access by the
DMAC or DTC.
• Priority
When the same page is accessed from different buses simultaneously, the access is processed
according to the priority. The priority is I bus > M bus > F bus.
Rev. 1.00 Jun. 26, 2008 Page 1490 of 1692
REJ09B0393-0100