SH7280 Datasheet, PDF (228/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 8 Data Transfer Controller (DTC)
Figure 8.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to
the data area*.
Note: When the transfer information is stored in the on-chip RAM, the RAME bit in RAMCR
must be set to 1.
INTC
On-chip
memory
On-chip
peripheral
module
Interrupt
request
CPU interrupt
request
Interrupt source
clear request
DTC
Register
control
Activation
control
CPU/DTC
request
determination
Interrupt
control
MRA
MRB
SAR
DAR
CRA
CRB
DTCERA to
DTCERE
DTCCR
DTCVBR
External
memory
Bus interface
External device
(memory mapped)
Bus state
controller
[Legend]
MRA, MRB:
DTC mode registers A, B
SAR:
DTC source address register
DAR:
DTC destination address register
CRA, CRB:
DTC transfer count registers A, B
DTCERA to DTCERE: DTC enable registers A to E
DTCCR:
DTC control register
DTCVBR:
DTC vector base register
Figure 8.1 Block Diagram of DTC
Rev. 1.00 Jun. 26, 2008 Page 198 of 1692
REJ09B0393-0100