SH7280 Datasheet, PDF (413/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 10 Direct Memory Access Controller (DMAC)
10.2 Input/Output Pins
The external pins for DMAC are described below. Table 10.1 lists the configuration of the pins
that are connected to external bus. DMAC has pins for four channels (CH0 to CH3) for SH7286
and two channels (CH0 and CH1) for SH7243 and SH7285, as the external bus use.
Table 10.1 Pin Configuration
Channel Name
Abbreviation I/O
0
DMA transfer request DREQ0
I
DMA transfer request DACK0
O
acknowledge
1
DMA transfer request DREQ1
I
DMA transfer request DACK1
O
acknowledge
2
DMA transfer request DREQ2
I
DMA transfer request DACK2
O
acknowledge
3
DMA transfer request DREQ3
I
DMA transfer request DACK3
O
acknowledge
0
DMA transfer end TEND0
O
1
DMA transfer end TEND1
O
Function
DMA transfer request input from an
external device to channel 0
DMA transfer request acknowledge
output from channel 0 to an external
device
DMA transfer request input from an
external device to channel 1
DMA transfer request acknowledge
output from channel 1 to an external
device
DMA transfer request input from an
external device to channel 2 (only in
SH7286)
DMA transfer request acknowledge
output from channel 2 to an external
device (only in SH7286)
DMA transfer request input from an
external device to channel 3 (only in
SH7286)
DMA transfer request acknowledge
output from channel 3 to an external
device (only in SH7286)
DMA transfer end output for channel 0
DMA transfer end output for channel 1
Rev. 1.00 Jun. 26, 2008 Page 383 of 1692
REJ09B0393-0100