SH7280 Datasheet, PDF (368/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
(6) Single Write
A write access ends in one cycle when the data bus width is larger than or equal to access size. As
a single write or burst write with burst length 1 is set in SDRAM, only the required data is output.
The write access that ends in one cycle is called single write. Figure 9.21 shows the single write
basic timing.
CK
A25 to A0
A12/A11*¹
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*²
Tr
Tc1 Trwl
Tap
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.21 Single Write Basic Timing (Auto-Precharge)
Rev. 1.00 Jun. 26, 2008 Page 338 of 1692
REJ09B0393-0100