SH7280 Datasheet, PDF (429/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 10 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Descriptions
1
TE
0
R/(W)* Transfer End Flag
This bit is set to 1 when DMATCR becomes 0 and
DMA transfer ends.
The TE bit is not set to 1 in the following cases.
• DMA transfer ends due to an NMI interrupt or
DMA address error before DMATCR becomes 0.
• DMA transfer is ended by clearing the DE bit and
DME bit in DMA operation register (DMAOR).
To clear the TE bit, write 0 after reading TE = 1.
Even if the DE bit is set to 1 while this bit is set to 1,
transfer is not enabled.
0: During the DMA transfer or DMA transfer has been
terminated
[Clearing condition]
• Writing 0 after reading TE = 1
1: DMA transfer ends by the specified count
(DMATCR = 0)
0
DE
0
R/W DMA Enable
Enables or disables the DMA transfer. In auto-request
mode, DMA transfer starts by setting the DE bit and
DME bit in DMAOR to 1. In this case, all of the bits
TE, NMIF in DMAOR, and AE must be 0. In an
external request or peripheral module request, DMA
transfer starts if DMA transfer request is generated by
the devices or peripheral modules after setting the
bits DE and DME to 1. In this case, however, all of the
bits TE, NMIF, and AE must be 0 as in the case of
auto-request mode. Clearing the DE bit to 0 can
terminate the DMA transfer.
0: DMA transfer disabled
1: DMA transfer enabled
Note: * Only 0 can be written to clear the flag after 1 is read.
Rev. 1.00 Jun. 26, 2008 Page 399 of 1692
REJ09B0393-0100