SH7280 Datasheet, PDF (145/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 5 Exception Handling
5.8 Stack Status after Exception Handling Ends
The status of the stack after exception handling ends is as shown in table 5.11.
Table 5.11 Stack Status After Exception Handling Ends
Exception Type
Address error
Stack Status
SP
Address of instruction
after executed instruction
SR
32 bits
32 bits
Interrupt
SP
Address of instruction
after executed instruction
SR
32 bits
32 bits
Register bank error (overflow)
SP
Address of instruction
after executed instruction
SR
32 bits
32 bits
Register bank error (underflow)
SP
Start address of relevant
RESBANK instruction
SR
32 bits
32 bits
Trap instruction
SP
Address of instruction
after TRAPA instruction
SR
32 bits
32 bits
Slot illegal instruction
Jump destination address
SP _{of delayed branch instruction} 32 bits
SR
32 bits
Rev. 1.00 Jun. 26, 2008 Page 115 of 1692
REJ09B0393-0100