SH7280 Datasheet, PDF (958/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 19 I²C Bus Interface 3 (IIC3)
19.3 Register Descriptions
The I²C bus interface 3 has the following registers.
Table 19.2 Register Configuration
Register Name
I²C bus control register 1
I²C bus control register 2
I²C bus mode register
I²C bus interrupt enable register
I²C bus status register
Slave address register
I²C bus transmit data register
I²C bus receive data register
NF2CYC register
Abbreviation
ICCR1
ICCR2
ICMR
ICIER
ICSR
SAR
ICDRT
ICDRR
NF2CYC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial
Value
H'00
H'7D
H'38
H'00
H'00
H'00
H'FF
H'FF
H'00
Address
H'FFFEE000
H'FFFEE001
H'FFFEE002
H'FFFEE003
H'FFFEE004
H'FFFEE005
H'FFFEE006
H'FFFEE007
H'FFFEE008
Access
Size
8
8
8
8
8
8
8
8
8
Rev. 1.00 Jun. 26, 2008 Page 928 of 1692
REJ09B0393-0100