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| SH7280 Datasheet, PDF (109/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family | |||
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Section 4 Clock Pulse Generator (CPG)
Table 4.3 Relationship between Clock Operating Mode and Frequency Range
PLL
FRQCR/MCLKCR/ACLKCR
Multipli-
Division Ratio Setting
cation
Ratio IÏ BÏ PÏ MÏ AÏ IÏ
Ã8
1/4 1/4 1/8 1/4 1/4 2
1/4 1/4 1/4 1/4 1/4 2
1/2 1/4 1/8 1/4 1/4 4
1/2 1/4 1/8 1/2 1/4 4
1/2 1/4 1/4 1/4 1/4 4
1/2 1/4 1/4 1/2 1/4 4
1/2 1/2 1/8 1/4 1/4 4
1/2 1/2 1/8 1/2 1/8 4
1/2 1/2 1/8 1/2 1/2 4
1/2 1/2 1/4 1/4 1/4 4
1/2 1/2 1/4 1/2 1/4 4
1/2 1/2 1/4 1/2 1/2 4
1/2 1/2 1/2 1/2 1/2 4
1/1 1/4 1/8 1/4 1/4 8
1/1 1/4 1/8 1/2 1/4 8
1/1 1/4 1/8 1/1 1/4 8
1/1 1/4 1/4 1/4 1/4 8
1/1 1/4 1/4 1/2 1/4 8
1/1 1/4 1/4 1/1 1/4 8
1/1 1/2 1/8 1/4 1/4 8
1/1 1/2 1/8 1/2 1/4 8
1/1 1/2 1/8 1/2 1/2 8
1/1 1/2 1/8 1/1 1/4 8
1/1 1/2 1/8 1/1 1/2 8
1/1 1/2 1/4 1/4 1/4 8
1/1 1/2 1/4 1/2 1/4 8
1/1 1/2 1/4 1/2 1/2 8
1/1 1/2 1/4 1/1 1/4 8
1/1 1/2 1/4 1/1 1/2 8
1/1 1/2 1/2 1/2 1/2 8
1/1 1/2 1/2 1/1 1/2 8
Clock Ratio
Clock Frequency (MHz)*
BÏ PÏ MÏ AÏ Input Clock IÏ BÏ PÏ MÏ AÏ
2 1 2 2 10
20 20 10 20 20
2222
20 20 20 20 20
2122
40 20 10 20 20
2142
40 20 10 40 20
2222
40 20 20 20 20
2242
40 20 20 40 20
4122
40 40 10 20 20
4142
40 40 10 40 20
4144
40 40 10 40 40
4222
40 40 20 20 20
4242
40 40 20 40 20
4244
40 40 20 40 40
4444
40 40 40 40 40
2122
80 20 10 20 20
2142
80 20 10 40 20
2182
80 20 10 80 20
2222
80 20 20 20 20
2242
80 20 20 40 20
2282
80 20 20 80 20
4122
80 40 10 20 20
4142
80 40 10 40 20
4144
80 40 10 40 40
4182
80 40 10 80 20
4184
80 40 10 80 40
4222
80 40 20 20 20
4242
80 40 20 40 20
4244
80 40 20 40 40
4282
80 40 20 80 20
4284
80 40 20 80 40
4444
80 40 40 40 40
4484
80 40 40 80 40
Rev. 1.00 Jun. 26, 2008 Page 79 of 1692
REJ09B0393-0100
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