SH7280 Datasheet, PDF (1364/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
25.3.7 USBEP0i Data Register (USBEPDR0i)
USBEPDR0i is an 8-byte transmit FIFO buffer for endpoint 0, holding one packet of transmit data
for control IN. Transmit data is fixed by writing one packet of data and setting the EP0iPKTE bit
in the trigger register. When an ACK handshake is returned from the host after the data has been
transmitted, bit 0 (EP0iTS) in USB interrupt flag register 0 is set.
USBEPDR0i can be initialized by means of the EP0iCLR bit in USBFCLR.
Bit: 7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value: -
-
-
-
-
-
-
-
R/W: W W W W W W W W
Bit
7 to 0
Bit Name
D7 to D0
Initial
Value
R/W Description
Undefined W Data register for control IN transfer
25.3.8 USBEP0o Data Register (USBEPDR0o)
USBEPDR0o is an 8-byte receive FIFO buffer for endpoint 0. USBEPDR0o holds endpoint 0
receive data other than setup commands. When data is received normally, the EP0oTS bit in USB
interrupt flag register 0 is set, and the number of receive bytes is indicated in the EP0o receive
data size register. After the data has been read, setting the EP0oRDFN bit in the trigger register
enables the next packet to be received.
USBEPDR0o can be initialized by means of the EP0oCLR bit in USBFCLR.
Bit: 7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value: -
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
Bit
7 to 0
Bit Name
D7 to D0
Initial
Value
R/W Description
Undefined R Data register for control OUT transfer
Rev. 1.00 Jun. 26, 2008 Page 1334 of 1692
REJ09B0393-0100