SH7280 Datasheet, PDF (45/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 1 Overview
Classification
Interrupts
Address bus
Data bus
Bus control
Symbol
I/O Name
Function
NMI
Input Non-maskable Non-maskable interrupt request pin.
interrupt
Fix it high when not in use.
IRQ7 to IRQ0
IRQOUT
Input
Interrupt
requests 7 to 0
Maskable interrupt request pins.
Level-input or edge-input detection
can be selected. When the edge-input
detection is selected, the rising edge,
falling edge, or both edges can also
be selected.
Output Interrupt request Indicates that an interrupt has
output
occurred, enabling external devices to
be informed of an interrupt occurrence
even while the bus mastership is
released.
A25 to A0
Output Address bus
Outputs addresses. (A25 to A21 are
available only in the SH7286.)
D31 to D0
I/O Data bus
CS7 to CS0
RD
Output Chip select 7
to 0
Output Read
RD/WR
Output Read/write
Bidirectional data bus. (D31 to D16
are available only in the SH7286.)
Chip-select signals for external
memory or devices.
Indicates that data is read from an
external device.
Read/write signal.
BS
AH
FRAME
WAIT
Output Bus start
Output Address hold
Output Frame signal
Input Wait
Bus-cycle start signal.
Address hold timing signal for the
device that uses the address/data-
multiplexed bus.
In burst MPX-I/O interface mode,
negated before the last bus cycle to
indicate that the next bus cycle is the
last access (only in SH7286)
Input signal for inserting a wait cycle
into the bus cycles during access to
the external space.
WRHH
Output Write to HH byte Indicates a write access to bits 31 to
24 of data of external memory or
device (only in SH7286).
WRHL
Output Write to HL byte Indicates a write access to bits 23 to
16 of data of external memory or
device (only in SH7286).
Rev. 1.00 Jun. 26, 2008 Page 15 of 1692
REJ09B0393-0100