SH7280 Datasheet, PDF (46/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 1 Overview
Classification Symbol
Bus control
WRH
WRL
DQMUU
DQMUL
DQMLU
DQMLL
RASU
CASU
RASL
CASL
CKE
REFOUT
Direct memory DREQ0 to
access controller DREQ3
(DMAC)
DACK0 to
DACK3
TEND1,
TEND0
I/O
Name
Function
Output Write to upper Indicates a write access to bits 15 to 8
byte
of data of external memory or device.
Output Write to lower Indicates a write access to bits 7 to 0
byte
of data of external memory or device.
Output HH byte
selection
Selects bits D31 to D24 when SDRAM
is connected (only in SH7286).
Output HL byte
selection
Selects bits D23 to D16 when SDRAM
is connected (only in SH7286).
Output Upper byte
selection
Selects bits D15 to D8 when SDRAM
is connected.
Output
Output
Lower byte
selection
RAS
Output CAS
Selects bits D7 to D0 when SDRAM is
connected.
Connected to the RAS pin when
SDRAM is connected (only in
SH7286).
Connected to the CAS pin when
SDRAM is connected (only in
SH7286).
Output RAS
Connected to the RAS pin when
SDRAM is connected.
Output CAS
Connected to the CAS pin when
SDRAM is connected.
Output CK enable
Connected to the CKE pin when
SDRAM is connected.
Output Refresh request Request signal output for refresh
output
execution while the bus mastership is
released.
Input
DMA-transfer
request
Input pins to receive external requests
for DMA transfer (DREQ2 and DREQ3
are only in SH7286).
Output
DMA-transfer
request accept
Output pins for signals indicating
acceptance of external requests from
external devices (DACK2 and DACK3
are only in SH7286).
Output DMA-transfer Output pins for DMA transfer end.
end output
Rev. 1.00 Jun. 26, 2008 Page 16 of 1692
REJ09B0393-0100