SH7280 Datasheet, PDF (1535/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 28 Power-Down Modes
28.3.7 System Control Register 1 (SYSCR1)
SYSCR1 is an 8-bit readable/writable register that enables or disables access to the on-chip RAM.
SYSCR1 is initialized to H'FF by a power-on reset but retains its previous value by a manual reset
or in software standby mode. Only byte access is possible.
When an RAME bit is set to 1, the corresponding on-chip RAM area is enabled. When an RAME
bit is cleared to 0, the corresponding on-chip RAM area cannot be accessed. In this case, an
undefined value is returned when reading data or fetching an instruction from the on-chip RAM,
and writing to the on-chip RAM is ignored. The initial value of an RAME bit is 1.
Note that when clearing the RAME bit to 0 to disable the on-chip RAM, be sure to execute an
instruction to read from or write to the same arbitrary address in each page before setting the
RAME bit. If such an instruction is not executed, the data last written to each page may not be
written to the on-chip RAM. Furthermore, an instruction to access the on-chip RAM should not be
located immediately after the instruction to write to SYSCR1. If an on-chip RAM access
instruction is set, normal access is not guaranteed.
To enable the on-chip RAM by setting the RAME bit to 1, place an instruction to read data from
SYSCR1 immediately after an instruction to write to SYSCR1. If an instruction to access the on-
chip RAM is placed immediately after the instruction to write to SYSCR1, normal access is not
guaranteed.
Bit: 7
6
5
4
3
2
1
0
-
-
-
- RAME3 RAME2 RAME1 RAME0
Initial value: 1
1
1
1
1
1
1
1
R/W: R
R
R
R R/W R/W R/W R/W
Rev. 1.00 Jun. 26, 2008 Page 1505 of 1692
REJ09B0393-0100