SH7280 Datasheet, PDF (279/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
Name
WRL/DQMLL
RASL, RASU
CASL, CASU
CKE
WAIT
BREQ
BACK
REFOUT
MD0
I/O
Function
Output Indicates that D7 to D0 are being written to.
Connected to the byte select signal when a SRAM with byte selection
is connected.
Functions as the select signals for D7 to D0 when SDRAM is
connected.
Output Connected to RAS pin when SDRAM is connected (RASU is available
only in the SH7286).
Output Connected to CAS pin when SDRAM is connected (CASU is available
only in the SH7286).
Output Connected to CKE pin when SDRAM is connected.
Input External wait input
Input Bus request input
Output Bus enable output
Output Refresh request output in bus-released state
Input
Selects bus width of area 0.
8 or 16 bits: SH7285 and SH7243
16 or 32 bits: SH7286
It also selects the on-chip ROM enabled or disabled mode and external
bus access enabled or disabled mode.
Rev. 1.00 Jun. 26, 2008 Page 249 of 1692
REJ09B0393-0100