SH7280 Datasheet, PDF (1384/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
Data Stage (Control-OUT): The application first analyzes command data from the host in the
setup stage, and determines the subsequent data stage direction. If the result of command data
analysis is that the data stage is OUT-transfer, the application waits for data from the host, and
after data is received (USBIFR0/EP0oTS = 1), reads data from the FIFO. Next, the application
writes 1 to the EP0o read complete bit, empties the receive FIFO, and waits for reception of the
next data.
The end of the data stage is identified when the host transmits an IN token and the status stage is
entered.
USB function
OUT token reception
Application
1 written
to USBTRG/EP0s
RDFN?
Yes
No
NACK
Data reception from host
ACK
Set EP0o reception
complete flag
(USBIFR0/EP0o TS = 1)
Interrupt request
Clear EP0o reception
complete flag
(USBIFR0/EP0o TS = 0)
OUT token reception
1 written
to USBTRG/EP0o
RDFN?
Yes
No
NACK
Read data from USBEP0o
receive data size register
(USBEPSZ0o)
Read data from USBEP0o
data register (USBEPDR0o)
Write 1 to EP0o read
complete bit
(USBTRG/EP0o RDFN = 1)
Figure 25.7 Data Stage (Control-OUT) Operation
Rev. 1.00 Jun. 26, 2008 Page 1354 of 1692
REJ09B0393-0100