SH7280 Datasheet, PDF (1358/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
Initial
Bit
Bit Name Value
3
SETUPTS 0
2
EP0oTS
0
1
EP0iTR
0
0
EP0iTS
0
R/W Description
R/W Setup Command Receive Complete
This bit is set to 1 when endpoint 0 receives normally
a setup command requiring decoding on the
application side, and returns an ACK handshake to
the host.
R/W EP0o Receive Complete
This bit is set to 1 when endpoint 0 receives data from
the host normally, stores the data in the FIFO buffer,
and returns an ACK handshake to the host.
R/W EP0i Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 0 is
received from the host. A NACK handshake is
returned to the host until data is written to the FIFO
buffer and packet transmission is enabled.
R/W EP0i Transmit Complete
This bit is set when data is transmitted to the host
from endpoint 0 and an ACK handshake is returned.
Rev. 1.00 Jun. 26, 2008 Page 1328 of 1692
REJ09B0393-0100