SH7280 Datasheet, PDF (986/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 19 I²C Bus Interface 3 (IIC3)
Notes: Follow the steps below to receive only one byte with MST = 1 specified. See figure 19.16
for the operation timing.
1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting)
2. Set MST = 1 while the RCVD bit in ICCR1 is 0. This causes the receive clock to be
output.
3. Check if the BC2 bit in ICMR is set to 1 and then set the RCVD bit in ICCR1 to 1.
This causes the SCL to be fixed to the high level after outputting one byte of the
receive clock.
SCL
SDA
(Input)
MST
1
2
Bit 0 Bit 1
7
8
1
Bit 6 Bit 7 Bit 0
7
8
1
2
Bit 6 Bit 7 Bit 0 Bit 1
TRS
RDRF
ICDRS
Data 1
Data 2
Data 3
ICDRR
Data 1
User
[2] Set MST
processing
(when outputting the clock)
[3] Read ICDRR
Figure 19.15 Receive Mode Operation Timing
Data 2
[3] Read ICDRR
Rev. 1.00 Jun. 26, 2008 Page 956 of 1692
REJ09B0393-0100