SH7280 Datasheet, PDF (1136/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 23 Pin Function Controller (PFC)
23.1.1 Port A I/O Registers H and L (PAIORH and PAIORL)
PAIORH and PAIORL are 16-bit readable/writable registers that are used to set the pins on port A
as inputs or outputs. Bits PA23IOR to PA21IOR, PA15IOR to PA0IOR correspond to pins PA23
to PA21, PA15 to PA0 (multiplexed port pin names except for the port names are abbreviated
here). PAIORH and PAIORL are enabled when the port A pins are functioning as general-purpose
inputs/outputs (PA23 to PA21 for PAIORH and PA15 to PA0 for PAIORL). In other states, they
are disabled. A given pin on port A will be an output pin if the corresponding bit in PAIORH or
PAIORL is set to 1, and an input pin if the bit is cleared to 0. However, bits 7 to 5 of PAIORH and
bits 11, 10 and 5 to 0 of PAIORL are disabled in SH7243, and bits 11 and 10 of PAIORL are
disabled in SH7285.
Bits 15 to 8, 4 to 0 of PAIORH are reserved. These bits are always read as 0. The write value
should always be 0.
The initial values of PAIORL and PAIORH are H'0000.
• Port A I/O Register H (PAIORH)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
PA23 PA22 PA21
IOR IOR IOR
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R
R
R
R
R
• Port A I/O Register L (PAIORL)
Bit: 15
PA15
IOR
Initial value: 0
R/W: R/W
14
PA14
IOR
0
R/W
13
PA13
IOR
0
R/W
12
PA12
IOR
0
R/W
11
PA11
IOR
0
R/W
10
PA10
IOR
0
R/W
9
PA9
IOR
0
R/W
8
PA8
IOR
0
R/W
7
PA7
IOR
0
R/W
6
PA6
IOR
0
R/W
5
PA5
IOR
0
R/W
4
PA4
IOR
0
R/W
3
PA3
IOR
0
R/W
2
PA2
IOR
0
R/W
1
PA1
IOR
0
R/W
0
PA0
IOR
0
R/W
Rev. 1.00 Jun. 26, 2008 Page 1106 of 1692
REJ09B0393-0100