SH7280 Datasheet, PDF (1378/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
• USI0 signal
The USI0 signal requests interrupts from the sources for which the corresponding bits in
interrupt select register 0 or 1 (UISR0 or UISR1) are cleared to 0. This signal is asserted if any
interrupt flag register bit that corresponds to the interrupt source assigned to this signal is set to
1.
• USI1 signal
The USI0 signal requests interrupts from the sources for which the corresponding bits in
interrupt select register 0 or 1 (UISR0 or UISR1) are set to 1. This signal is asserted if any
interrupt flag register bit that corresponds to the interrupt source assigned to this signal is set to
1.
Rev. 1.00 Jun. 26, 2008 Page 1348 of 1692
REJ09B0393-0100