SH7280 Datasheet, PDF (1494/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 26 Flash Memory
4. Bit rate
From the peripheral operating frequency (Pφ) and the bit rate (B), the value (= n) of the clock
select bits (CKS) in the serial mode register (SCSMR) and the value (= N) of the bit rate
register (SCBRR) are calculated, after which the error in the bit rate is calculated. This error is
checked to see if it is smaller than 4%. A result greater than or equal to 4% generates a bit rate
selection error. The following formula is use to calculate the error.
Error (%) = [
Pφ × 10⁶
] - 1 × 100
(N + 1) × B × 64 × 2^2n-1
When the new bit rate is selectable, the boot program returns an ACK code to the host and then
makes the register setting to select the new bit rate. The host then sends an ACK code at the
new bit rate, and the boot program responds to this with another ACK code, this time at the
new bit rate.
Acknowledge H'06
• Acknowledge H'06 (1 byte): The ACK code sent by the host to acknowledge the new bit rate.
Response
H'06
• Response H'06 (1 byte): The ACK code transferred in response to acknowledgement of the
new bit rate
The sequence of new bit rate selection is shown in figure 26.24.
Host
Wait for one-bit
period at the current
bit rate setting
Setting the new
bit rate
New bit rate setting
H'06 (ACK)
H'06 (ACK) at the new bit rate
H'06 (ACK) at the new bit rate
Boot program
New bit rate setting
Figure 26.24 Sequence of New Bit Rate Selection
Rev. 1.00 Jun. 26, 2008 Page 1464 of 1692
REJ09B0393-0100