SH7280 Datasheet, PDF (759/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 14 Compare Match Timer (CMT)
14.3 Operation
14.3.1 Interval Count Operation
When an internal clock is selected with the CKS[1:0] bits in CMCSR and the STR bit in CMSTR
is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and
CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the
CMIE bit in CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested.
CMCNT then starts counting up again from H'0000.
Figure 14.2 shows the operation of the compare match counter.
CMCNT value
CMCOR
Counter cleared by compare
match with CMCOR
H'0000
Time
Figure 14.2 Counter Operation
14.3.2 CMCNT Count Timing
One of four clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) obtained by dividing the peripheral clock
(Pφ) can be selected with the CKS[1:0] bits in CMCSR. Figure 14.3 shows the timing.
Peripheral clock
(Pφ)
Count clock
CMCNT
Clock
N
Clock
N+1
N
Figure 14.3 Count Timing
N+1
Rev. 1.00 Jun. 26, 2008 Page 729 of 1692
REJ09B0393-0100