SH7280 Datasheet, PDF (112/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 4 Clock Pulse Generator (CPG)
Initial
Bit
Bit Name Value R/W Description
15 to 11 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 8 STC[2:0] 011
R/W Bus Clock (Bφ) Frequency Division Ratio
These bits specify the frequency division ratio of the
bus clock.
000: × 1
001: × 1/2
010: Setting prohibited
011: × 1/4
100: Setting prohibited
101: × 1/8
Others: Setting prohibited
7

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4 IFC[2:0]
011
R/W Internal Clock (Iφ) Frequency Division Ratio
These bits specify the frequency division ratio of the
internal clock.
000: × 1
001: × 1/2
010: Setting prohibited
011: × 1/4
100: Setting prohibited
101: × 1/8
Others: Setting prohibited
3

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Jun. 26, 2008 Page 82 of 1692
REJ09B0393-0100