SH7280 Datasheet, PDF (1372/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
25.3.16 USB Data Status Register (USBDASTS)
USBDASTS indicates whether the transmit FIFO buffers contain valid data. A bit is set to 1 when
data is written to the corresponding FIFO buffer and the packet enable state is set. This bit is
cleared when all data has been transmitted to the host.
In the case of dual-FIFO buffer for endpoint 2, this bit is cleared when all data on two FIFOs has
been transmitted to the host.
USBDASTS can be initialized to H'00 by a power-on reset.
Bit: 7
6
5
4
3
2
1
0
-
- EP3DE EP2DE -
-
- EP0iDE
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit
7, 6
5
4
3 to 1
0
Bit Name

Initial
Value
All 0
EP3DE
0
EP2DE
0

All 0
EP0iDE
0
R/W Description
R
Reserved
The write value should always be 0.
R
EP3 Data Present
This bit is set when the endpoint 3 FIFO buffer
contains valid data.
R
EP2 Data Present
This bit is set when the endpoint 2 FIFO buffer
contains valid data
R
Reserved
The write value should always be 0.
R
EP0i Data Present
This bit is set when the endpoint 0 FIFO buffer
contains valid data.
Rev. 1.00 Jun. 26, 2008 Page 1342 of 1692
REJ09B0393-0100