SH7280 Datasheet, PDF (785/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 16 Serial Communication Interface (SCI)
Channel
4
(only for
SH7286
and
SH7285)
Register Name
Serial mode register_4
Bit rate register_4
Serial control register_4
Transmit data register_4
Serial status register_4
Receive data register_4
Serial direction control
register_4
Serial port register_4
Abbrevia-
tion
R/W
SCSMR_4 R/W
SCBRR_4 R/W
SCSCR_4 R/W
SCTDR_4 
SCSSR_4 R/W
SCRDR_4 
SCSDCR_4 R/W
Initial
Value
H'00
H'FF
H'00

H'84

H'F2
SCSPTR_4 R/W H'0x
Address
H'FFFFA000
H'FFFFA002
H'FFFFA004
H'FFFFA006
H'FFFFA008
H'FFFFA00A
H'FFFFA00C
H'FFFFA00E
Access
Size
8
8
8
8
8
8
8
8
16.3.1 Receive Shift Register (SCRSR)
SCRSR receives serial data. Data input at the RXD pin is loaded into SCRSR in the order
received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received,
it is automatically transferred to SCRDR. The CPU cannot read or write to SCRSR directly.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: -
-
-
-
-
-
-
-
16.3.2
Receive Data Register (SCRDR)
SCRDR is a register that stores serial receive data. After receiving one byte of serial data, the SCI
transfers the received data from the receive shift register (SCRSR) into SCRDR for storage and
completes operation. After that, SCRSR is ready to receive data.
Since SCRSR and SCRDR work as a double buffer in this way, data can be received continuously.
SCRDR is a read-only register and cannot be written to by the CPU.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: -
-
-
-
-
-
-
-
Rev. 1.00 Jun. 26, 2008 Page 755 of 1692
REJ09B0393-0100