SH7280 Datasheet, PDF (1370/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
25.3.15 USB Trigger Register (USBTRG)
USBTRG generates one-shot triggers to control the transmit/receive sequence for each endpoint.
USBTRG can be initialized to H'00 by a power-on reset.
Bit: 7
6
5
4
3
2
1
0
-
EP3 EP1 EP2
-
EP0s EP0o EP0i
PKTE RDFN PKTE
RDFN RDFN PKTE
Initial value: 0
0
0
0
0
0
0
0
R/W: -
WWW
-
WWW
Initial
Bit
Bit Name Value R/W Description
7

0

Reserved
This bit is always read as 0. The write value should
always be 0.
6
EP3PKTE 0
W
EP3 Packet Enable
After one packet of data has been written to the
endpoint 3 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
5
EP1RDFN 0
W
EP1 Read Complete
Write 1 to this bit after one packet of data has been
read from the endpoint 1 FIFO buffer. The endpoint 1
receive FIFO buffer has a dual-FIFO configuration.
Writing 1 to this bit initializes the FIFO that was read,
enabling the next packet to be received.
4
EP2PKTE 0
W
EP2 Packet Enable
After one packet of data has been written to the
endpoint 2 FIFO buffer, the transmit data is fixed by
writing 1 to this bit.
3

0

Reserved
The write value should always be 0.
Rev. 1.00 Jun. 26, 2008 Page 1340 of 1692
REJ09B0393-0100