SH7280 Datasheet, PDF (1086/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
(4) Abort Acknowledge Register (ABACK0)
The ABACK0 is a 16-bit read / conditionally-write registers. This register is used to signal to the
CPU that a mailbox transmission has been aborted as per its request. When an abort has succeeded
the RCAN-ET sets the corresponding bit in the ABACK register. The CPU may clear the Abort
Acknowledge bit by writing a '1' to the corresponding bit location. Writing a '0' has no effect. An
ABACK bit position is set by the RCAN-ET to acknowledge that a TXPR bit has been cleared by
the corresponding TXCR bit.
• ABACK0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
ABACK0[15:1]
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* -
Note : * Only when writing a ‘1’ to clear.
Bit 15 to 1 — notifies that the requested transmission cancellation of the corresponding Mailbox
has been performed successfully. The bit 15 to 1 corresponds to Mailbox-15 to 1 respectively.
Bit[15:1]:ABACK0 Description
0
[Clearing Condition] Writing ‘1’ (Initial value)
1
Corresponding Mailbox has cancelled transmission of message (Data or
Remote Frame)
[Setting Condition] Completion of transmission cancellation for corresponding
mailbox
Bit 0 — This bit is always ‘0’ as this is a receive-only mailbox. Writing a '1' to this bit position
has no effect and always read back as a ‘0’.
(5) Data Frame Receive Pending Register (RXPR0)
The RXPR0 is a 16-bit read / conditionally-write registers. The RXPR is a register that contains
the received Data Frames pending flags associated with the configured Receive Mailboxes. When
a CAN Data Frame is successfully stored in a receive mailbox the corresponding bit is set in the
RXPR. The bit may be cleared by writing a '1' to the corresponding bit position. Writing a '0' has
no effect. However, the bit may only be set if the mailbox is configured by its MBC (Mailbox
Configuration) to receive Data Frames. When a RXPR bit is set, it also sets IRR1 (Data Frame
Received Interrupt Flag) if its MBIMR (Mailbox Interrupt Mask Register) is not set, and the
interrupt signal is generated if IMR1 is not set. Please note that these bits are only set by receiving
Data Frames and not by receiving Remote frames.
Rev. 1.00 Jun. 26, 2008 Page 1056 of 1692
REJ09B0393-0100