SH7280 Datasheet, PDF (719/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 13 Port Output Enable 2 (POE2)
Section 13 Port Output Enable 2 (POE2)
The port output enable 2 (POE2) can be used to place the high-current pins (PE9/TIOC3B,
PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B, PE14/TIOC4C, PE15/TIOC4D, PE0/TIOC4AS,
PE1/TIOC4BS, PE2/TIOC4CS, PE3/TIOC4DS, PE5/TIOC3BS, PE6/TIOC3DS, PD15/TIOC4DS,
PD14/TIOC4CS, PD13/TIOC4BS, PD12/TIOC4AS, PD11/TIOC3DS, PD10/TIOC3BS,
PD24/TIOC4DS, PD25/TIOC4CS, PD26/TIOC4BS, PD27/TIOC4AS, PD28/TIOC3DS, and
PD29/TIOC3BS) and the pins for channel 0 of the MTU2 (PE0/TIOC0A, PE1/TIOC0B,
PE2/TIOC0C, and PE3/TIOC0D) in high-impedance state, depending on the change on the POE0
to POE8* input pins and the output status of the high-current pins, or by modifying register
settings. It can also simultaneously generate interrupt requests.
13.1 Features
• Each of the POE0 to POE8* input pins can be set for falling edge, Pφ/8 × 16, Pφ/16 × 16, or
Pφ/128 × 16 low-level sampling.
• High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance
state by POE0 to POE8* pin falling-edge or low-level sampling.
• High-current pins can be placed in high-impedance state when the high-current pin output
levels are compared and simultaneous active-level output continues for one cycle or more.
• High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance
state by modifying the POE2 register settings.
• Interrupts can be generated by input-level sampling or output-level comparison results.
The POE2 has input level detection circuits, output level comparison circuits, and a high-
impedance request/interrupt request generating circuit as shown in the block diagram of figure
13.1.
Note: * Only POE8, POE4, POE3, and POE0 are available in the SH7243.
Rev. 1.00 Jun. 26, 2008 Page 689 of 1692
REJ09B0393-0100