SH7280 Datasheet, PDF (111/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 4 Clock Pulse Generator (CPG)
4.4 Register Descriptions
The clock pulse generator has the following registers.
Table 4.4 Register Configuration
Register Name
Frequency control register
MTU2S clock frequency
control register
AD clock frequency control
register
Oscillation stop detection
control register
Abbreviation R/W
FRQCR
R/W
MCLKCR R/W
ACLKCR
R/W
OSCCR
R/W
Initial Value Address Access Size
H'0333
H'FFFE0010 16
H'43
H'FFFE0410 8
H'43
H'FFFE0414 8
H'00
H'FFFE001C 8
4.4.1 Frequency Control Register (FRQCR)
FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the
CK pin in software standby mode, the frequency multiplication ratio of PLL circuit 1, and the
frequency division ratio of the internal clock (Iφ) and peripheral clock (Pφ). FRQCR can be
accessed only in word units. After executing an instruction for modifying the FRQCR, be sure to
execute 32 NOP instructions. Especially when writing/erasing to the flush memory, execute the
NOP operation for 32Pφ clock after having confirmed the set value by reading the FRQCR.
FRQCR is initialized to H'0333 only by a power-on reset. FRQCR retains its previous value by a
manual reset or in software standby mode. The previous value is also retained when an internal
reset is triggered by an overflow of the WDT.
When switching the division ratio of bus clock frequency, the CK pin is fixed at low level for a
cycle of an input clock so as to prevent a hazard of switching.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
STC[2:0]
-
IFC[2:0]
-
PFC[2:0]
Initial value: 0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
R/W: R
R
R
R
R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W
Rev. 1.00 Jun. 26, 2008 Page 81 of 1692
REJ09B0393-0100