SH7280 Datasheet, PDF (265/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Clock (Bφ)
DTC activation
request 1
DTC activation
request 2
DTC request
Bus release timing
(setting 3)
Bus release timing
(setting 1)
Bus release timing
(setting 2)
Section 8 Data Transfer Controller (DTC)
Internal address
RW
RW
Vector Transfer information
read
read
Data
transfer
: Indicates bus mastership release timing.
Transfer
information
write
Vector Transfer information
read
read
Data
transfer
Transfer
information
write
: Bus mastership is only released for the external access request from the CPU.
Note: DTC request signal indicates the state of internal bus request after the DTC activation source is determined.
Figure 8.16 Example of DTC Operation Timing:
Conflict of Two Activation Requests in Normal Transfer Mode
(Activated by On-Chip Peripheral Module; Iφ : Bφ : Pφ = 1 : 1/2 : 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 Cycles)
Rev. 1.00 Jun. 26, 2008 Page 235 of 1692
REJ09B0393-0100