SH7280 Datasheet, PDF (162/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 6 Interrupt Controller (INTC)
6.3.7 USB-DTC Transfer Interrupt Request Register (USDTENDRR)
USDTENDRR is a 16-bit register that indicates USB-DTC transfer end interrupt requests, which
are on-chip peripheral module interrupts. Writing 0 to the RXF or TXF bit after reading RXF = 1
or TXF = 1 cancels the retained interrupt.
USDTENDRR is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RXF TXF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/(W)* R/(W)* R
R
R
R
R
R
R
R
R
R
R
R
R
R
Note: * Only 0 can be written to clear the flag after 1 is read.
Bit
15
14
13 to 0
Bit Name
RXF
TXF

Initial
Value
0
0
All 0
R/W
R/(W)*
R/(W)*
R
Description
EP1-FIFO Full DTC Transfer End Interrupt Request
0: EP1-FIFO full DTC transfer end interrupt request has
not occurred
[Clearing conditions]
• Cleared by reading RFX = 1, then writing 0 to RFX
• Cleared by executing EP1-FIFO full DTC transfer
end interrupt exception handling
1: EP1-FIFO full DTC transfer end interrupt request has
occurred
EP2-FIFO Empty DTC Transfer End Interrupt Request
0: EP2-FIFO empty DTC transfer end interrupt request
has not occurred
[Clearing conditions]
• Cleared by reading TFX = 1, then writing 0 to TFX
• Cleared by executing EP2-FIFO empty DTC
transfer end interrupt exception handling
1: EP2-FIFO empty DTC transfer end interrupt request
has occurred
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Jun. 26, 2008 Page 132 of 1692
REJ09B0393-0100