|
SH7280 Datasheet, PDF (402/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family | |||
|
◁ |
Section 9 Bus State Controller (BSC)
Table 9.19 Minimum Number of Idle Cycles on Internal Bus (CPU Operation)
CPU Operation
4:1
Write â write
2
Write â read
0
Read â write
2
Read â read
0
Clock Ratio (IÏ:BÏ)
2:1
1:1
2
3
0
1
2
3
0
1
Table 9.20 Minimum Number of Idle Cycles on Internal Bus (DMAC Operation)
Transfer Mode
DMAC Operation Dual Address
Single Address
Write â write
0
2
Write â read
0 or 2
0
Read â write
0
0
Read â read
0
2
Notes: 1. The write â write and read â read columns in dual address transfer indicate the cycles
in the divided access cycles.
2. For the write â read cycles in dual address transfer, 0 means different channels are
activated successively and 2 means when the same channel is activated successively.
3. The write â read and read â write columns in single address transfer indicate the case
when different channels are activated successively. The "write" means transfer from a
device with DACK to external memory and the "read" means transfer from external
memory to a device with DACK.
Rev. 1.00 Jun. 26, 2008 Page 372 of 1692
REJ09B0393-0100
|
▷ |