SH7280 Datasheet, PDF (44/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 1 Overview
Classification
Operating mode
control
System control
Symbol I/O Name
Function
MD1, MD0 Input Mode set
ASEMD0 Input Debugging
mode
Sets the operating mode. Do not
change the signal levels on these pins
during operation.
Enables the E10A-USB emulator
functions.
Input a high level to operate the LSI in
normal mode (not in debugging
mode). To operate it in debugging
mode, apply a low level to this pin on
the user system board.
FWE
RES
MRES
WDTOVF
BREQ
BACK
Input Flash memory
write enable
Pin for flash memory. Flash memory
can be protected against writing or
erasure through this pin.
Input Power-on reset This LSI enters the power-on reset
state when this signal goes low.
Input Manual reset
This LSI enters the manual reset state
when this signal goes low.
Output Watchdog timer Outputs an overflow signal from the
overflow
WDT.
Input Bus-mastership A low level is input to this pin when an
request
external device requests the release
of the bus mastership.
Output Bus-mastership
request
acknowledge
Indicates that the bus mastership has
been released to an external device.
Reception of the BACK signal informs
the device which has output the
BREQ signal that it has acquired the
bus.
Rev. 1.00 Jun. 26, 2008 Page 14 of 1692
REJ09B0393-0100