SH7280 Datasheet, PDF (422/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 10 Direct Memory Access Controller (DMAC)
10.3.4 DMA Channel Control Registers (CHCR)
The DMA channel control registers (CHCR) are 32-bit readable/writable registers that control
DMA transfer mode.
The DO, AM, AL, DL, and DS bits which specify the DREQ and DACK external pin functions
can be read and written to in channels 0 to 3, but they are reserved in channels 4 to 7. The TL bit
which specifies the TEND external pin function can be read and written to in channels 0 and 1, but
it is reserved in channels 2 to 7.
CHCR is initialized to H'00000000 by a reset and retains the value in software standby mode and
module standby mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TC
-
-
RLD
-
-
-
-
DO TL
-
-
HE HIE AM AL
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R
R R/W R
R
R
R R/W R/W R
R R/(W)* R/W R/W R/W
Bit:
Initial value:
R/W:
15 14
DM[1:0]
0
0
R/W R/W
13 12
SM[1:0]
0
0
R/W R/W
11
0
R/W
10 9
RS[3:0]
0
0
R/W R/W
8
0
R/W
7
DL
0
R/W
6
DS
0
R/W
5
TB
0
R/W
4
3
TS[1:0]
0
0
R/W R/W
2
1
0
IE
TE DE
0
0
0
R/W R/(W)* R/W
Note: * Only 0 can be written to clear the flag after 1 is read.
Bit
Bit Name
31
TC
30, 29 
Initial
Value
0
All 0
R/W Descriptions
R/W Transfer Count Mode
Specifies whether to transmit data once or for the
count specified in DMATCR by one transfer request.
Note that when this bit is set to 0, the TB bit must not
be set to 1 (burst mode). When the USB, RCAN, SSU,
SCIF_3, or IIC3 is selected for the transfer request
source, this bit (TC) must not be set to 1.
0: Transmits data once by one transfer request
1: Transmits data for the count specified in DMATCR
by one transfer request
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Jun. 26, 2008 Page 392 of 1692
REJ09B0393-0100