SH7280 Datasheet, PDF (786/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 16 Serial Communication Interface (SCI)
16.3.3
Transmit Shift Register (SCTSR)
SCTSR transmits serial data. The SCI loads transmit data from the transmit data register (SCTDR)
into SCTSR, then transmits the data serially from the TXD pin, LSB (bit 0) first. After
transmitting one data byte, the SCI automatically loads the next transmit data from SCTDR into
SCTSR and starts transmitting again. If the TDRE flag in the serial status register (SCSSR) is set
to 1, the SCI does not transfer data from SCTDR to SCTSR. The CPU cannot read or write to
SCTSR directly.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: -
-
-
-
-
-
-
-
16.3.4
Transmit Data Register (SCTDR)
SCTDR is an 8-bit register that stores data for serial transmission. When the SCI detects that the
transmit shift register (SCTSR) is empty, it moves transmit data written in the SCTDR into
SCTSR and starts serial transmission. If the next transmit data has been written to SCTDR during
serial transmission from SCTSR, the SCI can transmit data continuously. SCTDR can always be
written or read to by the CPU.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: -
-
-
-
-
-
-
-
16.3.5
Serial Mode Register (SCSMR)
SCSMR is an 8-bit register that specifies the SCI serial communication format and selects the
clock source for the baud rate generator.
The CPU can always read and write to SCSMR.
Bit: 7
C/A
Initial value: 0
R/W: R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
2
STOP MP
0
0
R/W R/W
1
0
CKS[1:0]
0
0
R/W R/W
Rev. 1.00 Jun. 26, 2008 Page 756 of 1692
REJ09B0393-0100