SH7280 Datasheet, PDF (1023/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 20 A/D Converter (ADC)
A/D conversion execution
ADST
ADST set*
ADST cleared*
ADF
AN0
AN1
AN2
AN3
ADDR0
ADDR1
ADF cleared*
Simultaneous sampling
Waiting for
conversion
S
OFC
A/D
H conversion
(1)
Waiting for
conversion
Simultaneous sampling
S
OFC
A/D
H conversion
(2)
Waiting for
conversion
Stop
S
Waiting for
conversion
Waiting for
conversion
OFC
Waiting for conversion
OFC
Waiting for conversion
Simultaneous sampling
Waiting for
conversion
S
OFC
H
H
Simultaneous sampling
Stop
A/D
Waiting for
conversion conversion
S
OFC
H
H
A/D
Waiting for
conversion conversion
S
Waiting for
conversion
(1)
(2)
Waiting for
conversion
OFC
Waiting for
conversion
A/D
conversion
Waiting for
conversion
OFC
(1)
Waiting for
conversion
A/D
conversion
(2)
Waiting for
conversion
A/D conversion result (AN0)
(1)
A/D conversion result (AN0)
(2)
ADDR2
ADDR3
[Legend]
OFC:
S:
H:
Offset canceling processing
Sampling
Holding
Note: * Instruction execution by software
A/D conversion result (AN2)
(1)
A/D conversion result (AN2)
(2)
A/D conversion result (AN3)
(1)
A/D conversion result (AN3)
(2)
[ADBYPSCR_0 settings]
OFC bit = 0
SH bit = 1
Figure 20.6 Example 1 of A/D Converter Operation (Continuous Scan Mode,
Sample-and-Hold Circuit Enabled, and Offset Canceling Circuit Enabled)
Rev. 1.00 Jun. 26, 2008 Page 993 of 1692
REJ09B0393-0100