SH7280 Datasheet, PDF (20/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

16.4 Operation .......................................................................................................................... 783
16.4.1 Overview .......................................................................................................... 783
16.4.2 Operation in Asynchronous Mode .................................................................... 785
16.4.3 Clock Synchronous Mode................................................................................. 796
16.4.4 Multiprocessor Communication Function ........................................................ 805
16.4.5 Multiprocessor Serial Data Transmission ......................................................... 807
16.4.6 Multiprocessor Serial Data Reception .............................................................. 808
16.5 SCI Interrupt Sources and DTC........................................................................................ 811
16.6 Serial Port Register (SCSPTR) and SCI Pins ................................................................... 812
16.7 Usage Notes ...................................................................................................................... 814
16.7.1 SCTDR Writing and TDRE Flag...................................................................... 814
16.7.2 Multiple Receive Error Occurrence .................................................................. 814
16.7.3 Break Detection and Processing ....................................................................... 815
16.7.4 Sending a Break Signal..................................................................................... 815
16.7.5 Receive Data Sampling Timing and Receive Margin
(Asynchronous Mode)....................................................................................... 815
16.7.6 Note on Using DTC .......................................................................................... 817
16.7.7 Note on Using External Clock in Clock Synchronous Mode............................ 817
16.7.8 Module Standby Mode Setting ......................................................................... 817
Section 17 Serial Communication Interface with FIFO (SCIF).......................... 819
17.1 Features............................................................................................................................. 819
17.2 Input/Output Pins.............................................................................................................. 821
17.3 Register Descriptions........................................................................................................ 822
17.3.1 Receive Shift Register (SCRSR) ...................................................................... 822
17.3.2 Receive FIFO Data Register (SCFRDR) .......................................................... 823
17.3.3 Transmit Shift Register (SCTSR) ..................................................................... 823
17.3.4 Transmit FIFO Data Register (SCFTDR)......................................................... 824
17.3.5 Serial Mode Register (SCSMR)........................................................................ 825
17.3.6 Serial Control Register (SCSCR)...................................................................... 828
17.3.7 Serial Status Register (SCFSR) ........................................................................ 832
17.3.8 Bit Rate Register (SCBRR) .............................................................................. 840
17.3.9 FIFO Control Register (SCFCR) ...................................................................... 847
17.3.10 FIFO Data Count Register (SCFDR)................................................................ 849
17.3.11 Serial Port Register (SCSPTR) ......................................................................... 850
17.3.12 Line Status Register (SCLSR) .......................................................................... 851
17.3.13 Serial Extended Mode Register (SCSEMR) ..................................................... 853
17.4 Operation .......................................................................................................................... 854
17.4.1 Overview .......................................................................................................... 854
17.4.2 Operation in Asynchronous Mode .................................................................... 856
Rev. 1.00 Jun. 26, 2008 Page xx of xxx