SH7280 Datasheet, PDF(245/1726 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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SH7280 Datasheet, PDF (245/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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Section 8 Data Transfer Controller (DTC)

Origin of

Activation

Source

Activation

Source

DTC Vector

Vector Address

Number Offset

DTCE*1

Transfer

Source

Transfer

Destination Priority

SSU

SSRXI

234

H'000007A8 DTCERD5 SSRDR0 to Any location*2 High

SSRDR3

SSTXI

235

H'000007AC DTCERD4 Any location*2 SSTDR0 to

SSTDR3

SCI4

RXI4

237

H'000007B4 DTCERD3 SCRDR_4

Any location*2

TXI4

238

H'000007B8 DTCERD2 Any location*2 SCTDR_4

SCI0

RXI0

241

H'000007C4 DTCERE15 SCRDR_0

Any location*2

TXI0

242

H'000007C8 DTCERE14 Any location*2 SCTDR_0

SCI1

RXI1

245

H'000007D4 DTCERE13 SCRDR_1

Any location*2

TXI1

246

H'000007D8 DTCERE12 Any location*2 SCTDR_1

SCI2

RXI2

249

H'000007E4 DTCERE11 SCRDR_2

Any location*2

TXI2

250

H'000007E8 DTCERE10 Any location*2 SCTDR_2

SCIF3

RXI3

254

H'000007F8 DTCERE9 SCFRDR_3 Any location*2

TXI3

255

H'000007FC DTCERE8 Any location*2 SCFTDR_3 Low

Notes: 1. The DTCE bits with no corresponding interrupt are reserved, and the write value should

always be 0.

2. An external memory, a memory-mapped external device, an on-chip memory, or an on-

chip peripheral module (except for DTC, BSC, UBC, AUD, FLASH, and DMAC) can be

selected as the source or destination. Note that at least either the source or destination

must be an on-chip peripheral module; transfer cannot be done among an external

memory, a memory-mapped external device, and an on-chip memory.

3. Read to a message control field in mailbox 0 by using a block transfer mode or etc.

Rev. 1.00 Jun. 26, 2008 Page 215 of 1692

REJ09B0393-0100

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